SDLS136 - DECEMBER 1972 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
The 'LS181 and 'S181 are arithmetic logic units (ALU)/function generatorsthat have a complexity of 75 equivalent gates on a monolithic chip. Thesecircuits perform 16 binary arithmetic operations on two 4-bit words as shownin Tables 1 and 2. These operations are selected by the four function-selectlines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straighttransfer. When performing arithmetic manipulations, the internal carries mustbe enabled by applying a low-level voltage to the mode control input (M).A full carry look-ahead scheme is made available in these devices for fast,simultaneous carry generation by means of two cascade-outputs (pins 15 and17) for the four bits in the package. When used in conjunction with the SN54S182or SN74S182 full carry look-ahead circuits, high-speed arithmetic operationscan be performed. The typical addition times shown above illustrate the littleadditional time required for addition of longer words when full carry look-aheadis employed. The method of cascading 'S182 circuits with these ALUs to providemulti-level full carry look-ahead is illustrated under typical applicationsdata for the 'S182.
If high speed is not of importance, a ripple-carry input (Cn)and a ripple-carry output (Cn+4) are available. However, the ripple-carrydelay has also been minimized so that arithmetic manipulations for small wordlengths can be performed without external circuitry.
The 'LS181 and 'S181 will accommodate active-high data if the pin designationsare interpreted as follows:
Subtraction is accomplished by 1's complement addition where the1's complement of the subtrahend is generated internally.The resultant outputis A – B – 1, which requires an end-around or forced carry toprovide A – B.
The 'LS181 or 'S181 can also be utilized as a comparator. The A = B outputis internally decoded from the function outputs (F0, F1, F2, F3) so that whentwo words of equal magnitude are applied at the A and B inputs, it will assumea high level to indicate equality (A = B). The ALU must be in the subtractmode with Cn = H when performing this comparison. The A = B outputis open-collector so that it can be wire-AND connected to give a comparisonfor more than four bits. The carry output (Cn+4) can also be usedto supply relative magnitude information. Again, the ALU must be placed inthe subtract mode by placing the function select inputs S3, S2, S1, S0 atL, H, H, L, respectively.
These circuits have been designed to not only incorporate all of the designer'srequirements for arithmetic operations, but also to provide 16 possible functionsof two Boolean variables without the use of external circuitry. These logicfunctions are selected by use of the four function-select inputs (S0, S1,S2, S3) with the mode-control input (M) at a high level to disable the internalcarry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusive-OR,NAND, AND, NOR, and OR functions.
Series 54, 54LS, and 54S devices are characterized for operation over thefull military temperature range of -55°C to 125°C; Series 74LS and74S devices are characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN54LS181, SN54S181, SN74LS181, SN74S181
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