SDLS134 - OCTOBER 1976 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These synchronous presettable counters feature an internal carry look-aheadfor cascading in high speed counting applications. The 'LS169B and 'S169 are4-bit binary counters. Synchronous operation is provided by having all flip-flopsclocked simultaneously so that the outputs change coincident with each otherwhen so instructed by the count-enable inputs and internal gating. This modeof operation helps eliminate the output counting spikes that are normallyassociated with asynchronous (ripple-clock) counters. A buffered clock inputtriggers the four master-slave flip-flops on the rising (positive-going) edgeof the clock waveform.
These counters are fully programmable; that is the outputs may each bepreset to either level. The load input circuitry allows loading with the carry-enableoutput of cascaded counters. As loading is synchronous, setting up a low levelat the load input disables the counter and causes the outputs to agree withthe data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bitsynchronous applications without additional gating. Instrumental in accomplishingthis function are two count-enable inputs and a carry output. Both count enableinputs (ENP\, ENT\) must be low to count. The directionof the count is determined by the level of the up/down input. When the inputis high, the counter counts up; when low, it counts down. Input ENT\is fed forward to enable the carry output. The carry output thus enabled willproduce a low-level output pulse with a duration approximately equal to thehigh portion of the QA output when counting up and approximatelyequal to the low portion of the QA output when counting down. Thislow-level overflow carry pulse can be used to enable successive cascaded stages.Transitions at the ENP\ or ENT\ inputs are allowed regardlessof the level of the clock input. All inputs are diode-clamped to minimizetransmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. Changes at controlinputs (ENP\, ENT\, LOAD\, U/D\) thatwill modify the operating mode have no effect until clocking occurs. The functionof the counter (whether enabled, disabled, loading, or counting) will be dictatedsolely by the conditions meeting the stable setup and hold times.
View more information about generic part numbers:SN54LS169B, SN54S169, SN74LS169B, SN74S169
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