SDLS130 - DECEMBER 1972 - REVISED MARCH 1988
Coyright © 1988, Texas Instruments Incorporated
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These monolithic, fully synchronous, programmable counters utilize Series54/74 TTL circuitry to achieve 32-megahertz typical maximum operating frequencies.These six-bit serial binary counters feature buffered clock, clear, and enableinputs to control the operation of the counter, and a strobe input to enableor inhibit the rate input/decoding AND-OR-INVERT gates. The outputs have additionalgating for cascading and transferring unity-count rates.
The counter is enabled when the clear, strobe, and enable inputs are low.With the counter enabled, the output frequency is equal to the input frequencymultiplied by the rate input M and divided by 64, ie.:
When the rate input is binary 0 (all rate inputs low), Z remains high.In order to cascade devices to perform 12-bit rate multiplication, the enableoutput is connected to the enable and strobe inputs of the next stage, theZ output of each stage is connected to the unity/cascade input of the otherstage, and the sub-multiple frequency is taken from the Y output.
The unity/cascade input, when connected to the clock input, may be utilizedto pass the clock frequency (inverted) to the Y output when the rate input/decodinggates are inhibited by the strobe. The unity/cascade input may also be usedas a control for the Y output.
View more information about generic part numbers:SN5497, SN7497
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