SN54376, SN74376 QUADRUPLE J-K\ FLIP-FLOPS

SDLS104 - OCTOBER 1976 - REVISED MARCH 1988

PRODUCTION DATA information is current as of publication date. Productsconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

features

Four J-K\ Flip-Flops in a Single Package … Can ReduceFF Package Count by 50%
Common Positive-Edge-Triggered Clocks with Hysteresis … Typically200 mV
Fully Buffered Outputs
Typical Clock Input Frequency … 45 MHz

description

These quadruple TTL J-K\ flip-flops incorporate a number of third-generationIC features that can simplify system design and reduce flip-flop package countby as much as 50%. They feature hysteresis at the clock input, fully bufferedoutputs, and direct clear capability. The positive-edge-triggered SN54376and SN74376 are directly compatible with most Series 54/74 MSI registers.

The SN54376 is characterized for operation over the full military temperaturerange of -55°C to 125°C; the SN74376 is characterized for operationfrom 0°C to 70°C.

Title: QUADRUPLE J-K(/) FLIP-FLOPS
Product Family: D-TYPE FLIP-FLOPS
Device Functionality: JK
Orderable Devices: SN54376J, SNJ54376J, SN74376N

View the complete PDF datasheet: sdls104.pdf (146 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN54376, SN74376

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