SN54276, SN74276 QUADRUPLE J-K\ FLIP-FLOPS

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features

• Four J-K\ Flip-Flops in a Single Package … Can ReduceFF Package Count by 50%
• Separate Negative-Edge-Triggered Clocks with Hysteresis … Typically200 mV
• Typical Clock Input Frequency … 50 MHz
• Fully Buffered Outputs

description

These quadruple TTL J-K\ flip-flops incorporate a number of third-generationIC features that can simplify system design and reduce flip-flop package countby up to 50%. They feature hysteresis at each clock input, fully bufferedoutputs, and direct clear capability, and are presettable through a bufferthat also features an input hysteresis loop. The negative-edge-triggeringclocks are directly compatible with earlier Series 54/74 single and dual pulse-triggeredflip-flops. These circuits can be used to emulate D- or T-type flip-flopsby hard-wiring the inputs, or to implement asynchronous sequential functions.

The SN54276 is characterized for operation over the full military temperaturerange of -55°C to 125°C; the SN74276 is characterized for operationfrom 0°C to 70°C.

View more information about generic part numbers:SN74276

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