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Data Sheet Abstract

SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPEFLIP-FLOP WITH CLEAR

SDLS090 - OCTOBER 1976 - REVISED MARCH 1988


features

description

These monolithic, positive-edge-triggered flip-flops utilize TTLcircuitry to implement D-type flip-flop logic with a direct clearinput.

Information at the D inputs meeting the setup time requirements istransferred to the Q outputs on the positive-going edge of the clockpulse. Clock triggering occurs at a particular voltage level and isnot directly related to the transition time of the positive-goingpulse. When the clock input is at either the high or low level, the Dinput signal has no effect at the output.

These flip-flops are guaranteed to respond to clock frequenciesranging form 0 to 30 megahertz while maximum clock frequency istypically 40 megahertz. Typical power dissipation is 39 milliwattsper flip-flop for the ´273 and 10 milliwatts for the´LS273.

 

 

 


Title: OCTAL D-TYPE FLIP-FLOP WITH CLEAR
Product Family: D-TYPE FLIP-FLOPS
Device Functionality: D-TYPE
Orderable Devices: JM38510/32501B2A, JM38510/32501BRA, JM38510/32501BSA, SN54LS273J, SNJ54LS273FK, SNJ54LS273J, SNJ54LS273W, SN74273N, SN74273N3, SN74LS273DW, SN74LS273DWR, SN74LS273J, SN74LS273N, SN74LS273N3, SN74LS273NSLE

View the complete PDF datasheet: sdls090.pdf (91 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN54LS273, SN74273, SN74LS273

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