



SDLS090 - OCTOBER 1976 - REVISED MARCH 1988
These monolithic, positive-edge-triggered flip-flops utilize TTLcircuitry to implement D-type flip-flop logic with a direct clearinput.
Information at the D inputs meeting the setup time requirements istransferred to the Q outputs on the positive-going edge of the clockpulse. Clock triggering occurs at a particular voltage level and isnot directly related to the transition time of the positive-goingpulse. When the clock input is at either the high or low level, the Dinput signal has no effect at the output.
These flip-flops are guaranteed to respond to clock frequenciesranging form 0 to 30 megahertz while maximum clock frequency istypically 40 megahertz. Typical power dissipation is 39 milliwattsper flip-flop for the ´273 and 10 milliwatts for the´LS273.
View more information about generic part numbers:SN54LS273, SN74273, SN74LS273
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.



