SDLS076 - MARCH 1974 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These 4-bit registers feature parallel inputs, parallel outputs, J-K\ serial inputs, shift/load (SH/LD\) control input, and adirect overriding clear. All inputs are buffered to lower the input driverequirements. The register has two modes of operation:
Parallel (broadside) loadShift (in the direction QA towardQD)
Parallel loading is accomplished by applying the four bits of data andtaking SH/LD\ low. The data is loaded into the associated flip-flopand appears at the outputs after the positive transition of the clock input.During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when SH/LD\ is high. Serialdata for this mode is entered at the J-K\ inputs. These inputs permitthe first stage to perform as a J-K\, D-, or T-type flip-flop asshown in the function table.
The high-performance 'S195, with a 105-megahertz typical maximum shift-frequency,is particularly attractive for very-high-speed data processing systems. Inmost cases existing systems can be upgraded merely by using this Schottky-clampedshift register.
View more information about generic part numbers:SN54195, SN54LS195A, SN54S195, SN74195, SN74LS195A, SN74S195
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