SDLS075 - MARCH 1974 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These bidirectional shift registers are designed to incorporate virtuallyall of the features a system designer may want in a shift register. The circuitcontains 46 equivalent gates and features parallel inputs, parallel outputs,right-shift and left-shift serial inputs, operating-mode-control inputs, anda direct overriding clear line. The register has four distinct modes of operation,namely:
Synchronous parallel loading is accomplished by applying the four bitsof data and taking both mode control inputs, S0 and S1, high. The data areloaded into the associated flip-flops and appear at the outputs after thepositive transition of the clock input. During loading, serial data flow isinhibited.
Shift right is accomplished synchronously with the rising edge of the clockpulse when S0 is high and S1 is low. Serial data for this mode is enteredat the shift-right data input. When S0 is low and S1 is high, data shiftsleft synchronously and new data is entered at the shift-left serial input.
Clocking of the shift register is inhibited when both mode control inputsare low. The mode controls of the SN54194/SN74194 should be changed only whilethe clock input is high.
View more information about generic part numbers:SN54194, SN54LS194A, SN54S194, SN74194, SN74LS194A, SN74S194
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