SDLS072 - DECEMBER 1972 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/downcounters having a complexity of 58 equivalent gates. The '191 and 'LS191 are4-bit binary counters and the '190 and 'LS190 are BCD counters. Synchronousoperation is provided by having all flip-flops clocked simultaneously so thatthe outputs change coincident with each other when so instructed by the steeringlogic. This mode of operation eliminates the output counting spikes normallyassociated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a low-to-hightransition of the clock input if the enable input is low. A high at the enableinput inhibits counting. Level changes at the enable input should be madeonly when the clock input is high. The direction of the count is determinedby the level of the down/up input. When low, the counter count up and whenhigh, it counts down. A false clock may occur if the down/up input changeswhile the clock is low. A false ripple carry may occur if both the clock andenable are low and the down/up input is high during a load pulse.
These counters are fully programmable; that is, the outputs may be presetto either level by placing a low on the load input and entering the desireddata at the data inputs. The output will change to agree with the data inputsindependently of the level of the clock input. This feature allows the countersto be used as modulo-N dividers by simply modifying the count length withthe preset inputs.
The clock, down/up, and load inputs are buffered to lower the drive requirementwhich significantly reduces the number of clock drivers, etc., required forlong parallel words.
Two outputs have been made available to perform the cascading function:ripple clock and maximum/minimum count. The latter output produces a high-leveloutput pulse with a duration approximately equal to one complete cycle ofthe clock when the counter overflows or underflows. The ripple clock outputproduces a low-level output pulse equal in width to the low-level portionof the clock input when an overflow or underflow condition exists. The counterscan be easily cascaded by feeding the ripple clock output to the enable inputof the succeeding counter if parallel clocking is used, or to the clock inputif parallel enabling is used. The maximum/minimum count output can be usedto accomplish look-ahead for high-speed operation.
Series 54' and 54LS' are characterized for operation over the full militarytemperature range of -55°C to 125°C; Series 74' and 74LS' are characterizedfor operation from 0°C to 70°C.
View more information about generic part numbers:SN54191, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191
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