SDLS063 - OCTOBER 1976 - REVISED MARCH 1988
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
The '166 and 'LS166A 8-bit shift registers are compatible with most otherTTL logic families. All '166 and 'LS166A inputs are buffered to lower thedrive requirements to one Series 54/74 or Series 54LS/74LS standard load,respectively. Input clamping diodes minimize switching transients and simplifysystem design.
These parallel-in or serial-in, serial-out shift registers have a complexityof 77 equivalent gates on a monolithic chip. They feature gated clock inputsand an overriding clear input. The parallel-in or serial-in modes are establishedby the shift/load input. When high, this input enables the serial data inputand couples the eight flip-flops for serial shifting with each clock pulse.When low, the parallel (broadside) data inputs are enabled and synchronousloading occurs on the next clock pulse. During parallel loading, serial dataflow is inhibited. Clocking is accomplished on the low-to-high-level edgeof the clock pulse through a two-input positive NOR gate permitting one inputto be used as a clock-enable or clock-inhibit function. Holding either ofthe clock inputs high inhibits clocking; holding either low enables the otherclock input. This, of course, allows the system clock to be free-running andthe register can be stopped on command with the other clock input. The clockinhibit input should be changed to the high level only while the clock inputis high. A buffered, direct clear input overrides all other inputs, includingthe clock, and sets all flip-flops to zero.
View more information about generic part numbers:SN54166, SN54LS166A, SN74166, SN74LS166A
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.