SDLS060 - OCTOBER 1976 - REVISED MARCH 1988
Copyright 1988, Texas Instruments Incorporated
PRODUCTION DATA documents contain information current as of publicationdate. Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily include testingof all parameters.
These synchronous, presettable counters feature an internal carry look-aheadfor application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A,and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163are 4-bit binary counters. Synchronous operation is provided by having allflip-flops clocked simultaneously so that the outputs change coincident witheach other when so instructed by the count-enable inputs and internal gating.This mode of operation eliminates the output counting spikes that are normallyassociated with asynchronous (ripple clock) counters, however counting spikesmay occur on the (RCO) ripple carry output. A buffered clock input triggersthe four flip-flops on the rising edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be presetto either level. As presetting is synchronous, setting up a low level at theload input disables the counter and causes the outputs to agree with the setupdata after the next clock pulse regardless of the levels of the enable inputs.Low-to-high transitions at the load input of the '160 thru '163 should beavoided when the clock is low if the enable inputs are high at or before thetransition. This restriction is not applicable to the 'LS160A thru 'LS163Aor 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161Ais asynchronous and a low level at the clear input sets all four of the flip-flopoutputs low regardless of the levels of clock, load, or enable inputs. Theclear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronousand a low level at the clear input sets all four of the flip-flop outputslow after the next clock pulse, regardless of the levels of the enable inputs.This synchronous clear allows the count length to be modified easily as decodingthe maximum count desired can be accomplished with one external NAND gate.The gate output is connected to the clear input to synchronously clear thecounter to 0000 (LLLL). Low-to-high transitions at the clear input of the'162 and '163 should be avoided when the clock is low if the enable and loadinputs are high at or before the transition.
The carry look-ahead circuitry provides for cascading counters for n-bitsynchronous applications without additional gating. Instrumental in accomplishingthis function are two count-enable inputs and a ripple carry output. Bothcount-enable inputs (P and T) must be high to count, and input T is fed forwardto enable the ripple carry output. The ripple carry output thus enabled willproduce a high-level output pulse with a duration approximately equal to thehigh-level portion of the QA output. This high-level overflow ripplecarry pulse can be used to enable successive cascaded stages. High-to-lowlevel transitions at the enable P or T inputs of the '160 thru '163 shouldoccur only when the clock input is high. Transitions at the enable P or Tinputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardlessof the level of the clock input.
'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clockcircuit. Changes at control inputs (enable P or T, or load) that will modifythe operating mode have no effect until clocking occurs. The function of thecounter (whether enabled, disabled, loading, or counting) will be dictatedsolely by the conditions meeting the stable setup and hold times.
View more information about generic part numbers:SN54163, SN54LS160A, SN54LS161A, SN54LS163A, SN54S163, SN74160, SN74161, SN74162, SN74163, SN74LS160A, SN74LS161A, SN74LS162A, SN74LS163A, SN74S162, SN74S163
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.