SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

SDFS048A - D2932, MARCH 1987 - REVISED OCTOBER 1993

features

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

description

The SN74F112 contains two independent J-K negative-edge-triggeredflip-flops. A low level at the preset () or clear () inputs sets or resets the outputsregardless of the levels of the other inputs. When and are inactive (high), data at the Jand K inputs meeting the setup time requirements is transferred tothe outputs on the negative-going edge of the clock pulse. Clocktriggering occurs at a voltage level and is not directly related tothe rise time of the clock pulse. Following the hold-time interval,data at the J and K inputs may be changed without affecting thelevels at the outputs. The SN74F112 can perform as a toggle flip-flopby tying J and K high.

The SN74F112 is characterized for operation from 0°C to70°C.

Title: DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
Product Family: OTHER FLIP-FLOPS
Device Functionality: J-K
Orderable Devices: SN74F112D, SN74F112DR, SN74F112N

View the complete PDF datasheet: sdfs048a.pdf (70 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74F112

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