SDFS011A - MARCH 1987 - REVISED OCTOBER 1993
These 8-bit latches feature 3-state outputs designed specificallyfor driving highly capacitive or relatively low-impedance loads. Theyare particularly suitable for implementing buffer registers, I/Oports, bidirectional bus drivers, and working registers.
The eight latches of the ´F573 are transparent D-typelatches. While the latch enable (LE) input is high, the Q outputsfollow the data (D) inputs. When the latch enable is taken low, the Qoutputs are latched at the logic levels set up at the D inputs.
A buffered output enable 
input can be used to place the eight outputs in either a normal logicstate (high or low logic levels) or a high- impedance state. In thehigh-impedance state, the outputs neither load nor drive the buslines significantly. The high-impedance state and increased driveprovide the capability to drive bus lines without need for interfaceor pullup components.
The output enable input does not affect the internal operations of the latches. Olddata can be retained or new data can be entered while the outputs arein the high-impedance state.
The SN54F573 is characterized for operation over the full militarytemperature range of -55°C to 125°C. The SN74F573 ischaracterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN74F573
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