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Data Sheet Abstract

SN74ALVC7803 512 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SDAS274 - JANUARY 1995


 

features

description

The SN74ALVC7803 FIFO is suited for buffering asynchronous datapaths at 50-MHz clock rates and 13-ns access times and is designedfor 3-V to 3.6-V VCC operation. The 56-pin shrinksmall-outline (DL) package offers greatly reduced board space overDIP, PLCC, and conventional SOIC packages. Two devices can beconfigured for bidirectional data buffering without additional logic.

The write clock (WRTCLK) and read clock (RDCLK) should be freerunning and can be asynchronous or coincident. Data is written tomemory on the rising edge of WRTCLK when WRTEN1 is high, is low, and input ready (IR) ishigh. Data is read from memory on the rising edge of RDCLK when ,, and arelow and output ready (OR) is high. The first word written to memoryis clocked through to the output buffer regardless of the ,, and levels. The OR flag indicates that valid data is presenton the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. must be asserted while at leastfour WRTCLK and four RDCLK rising edges occur to clear thesynchronizing registers. Resetting the FIFO initializes the IR, OR,and half-full (HF) flags low and the almost-full/almost-empty (AF/AE)flag high. The FIFO must be reset upon power up.


Title: 512 X 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
Product Family: CLOCKED FIFOS
Device Functionality: 512 X 18
Orderable Devices: SN74ALVC7803-20DL, SN74ALVC7803-25DL, SN74ALVC7803-40DL, SN74ALVC7803-20DL, SN74ALVC7803-25DL, SN74ALVC7803-40DL

View the complete PDF datasheet: sdas274.pdf (203 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVC7803, SN74ALVC7803-20, SN74ALVC7803-25, SN74ALVC7803-40

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

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