SDAS270 - DECEMBER 1994
These 8-bit D-type transparent latches feature 3-state outputsdesigned specifically for driving highly capacitive or relativelylow-impedance loads. They are particularly suitable for implementingbuffer registers, I/O ports, bidirectional bus drivers, and workingregisters.
While latch-enable (LE) input is high, the Q\ outputs follow thecomplements of the data (D) inputs. When LE is taken low, the Q\outputs are latched at the inverses of the levels set up at the Dinputs. The SN74ALS533A and SN74AS533A are functionally equivalent tothe SN74ALS373A and SN74AS373, except for having inverted outputs.
A buffered output-enable (
) input places the eight outputs in either a normallogic state (high or low logic levels) or a high-impedance state. Inthe high-impedance state, the outputs neither load nor drive the buslines significantly. The high-impedance state and increased driveprovide the capability to drive bus lines without interface or pullupcomponents.
does not affectthe internal operations of the latches. Old data can be retained ornew data can be entered while the outputs are off.
The SN74ALS533A and SN74AS533A are characterized for operationfrom 0°C to 70°C.
View more information about generic part numbers:SN74ALS533A, SN74AS533A
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