SDAS236A - DECEMBER 1982 - REVISED JANUARY 1995
These advanced Schottky devices are capable of performinghigh-speed arithmetic or logic comparisons on two 8-bit binary ortwo's complement words. Two fully decoded decisions about words P andQ are externally available at two outputs. These devices are fullyexpandable to any number of bits without external gates. To comparewords of longer lengths, the P > QOUT and P < QOUT outputs of astage handling less significant bits can be connected to the P >QIN and P < QIN inputs of the next stage handling more significantbits. The cascading paths are implemented with only a two-gate-leveldelay to reduce overall comparison times for long words. Twoalternative methods of cascading are shown in applicationinformation.
The latch is transparent when P latch-enable (PLE) input is high;the P-input port is latched
when PLE is low. This provides the designer with temporary storagefor the P-data word. The enable circuitry is implemented with minimaldelay times to enhance performance when cascaded for longer words.The PLE, P, and Q data inputs utilize pnp input transistors to reducethe low-level current input requirement to typically -0.25 mA, whichminimizes dc loading effects.
The SN54AS885 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The SN74AS885is characterized for operation from 0°C to 70°C.
In these cases, P > QOUT follows P > QIN and P <QOUT follows P < QIN.
AG = arithmetically greater than
View more information about generic part numbers:SN54AS885, SN74AS885
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