SDAS231 - D2825, JUNE 1984 - REVISED JANUARY 1986
These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers.
With the clock enable (CLKEN\) low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high will disable the clock buffer, thus latching the outputs. The 'AS823 has noninverting D inputs and the 'AS824 has inverting D inputs. Taking the CLR\ input low causes the nine Q outputs to go low independently of the clock.
A buffered output-control input OC\ can be used to place the nine outputs in either normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pullup components. The output control does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AS' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS' family is characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN54AS823, SN74AS823, SN74AS824
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