SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK

SDAS201 - D2661, DECEMBER 1982 - REVISED MAY 1986

features

• Fully Buffered to Offer Maximum isolation from External Disturbance
• Package Options include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
• Typical Maximum Clock Frequency 30 MHz
• Typical Power Dissipation per Flip-Flop 6 mW
• Dependable Texas Instruments Quality and Reliability

description

These devices contain two independent J-K negative-edge-triggeredflip-flops. A low level at the Preset or Clear inputs sets or resetsthe outputs regardless of the levels of the other inputs. When Presetand Clear are inactive (high), data at the J and K inputs meeting thesetup time requirements are transferred to the outputs on thenegative-going edge of the clock pulse. Clock triggering occurs at avoltage level and is not directly related to the fall time of theclock pulse. Following the hold time interval, data at the J and Kinputs may be changed without affecting the levels at the outputs.These versatile flip-flops can perform as toggle flip-flops by tyingJ and K high.

The SN54ALS114A is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ALS114A is characterized for operation from 0°C to70°C.

View more information about generic part numbers:SN74ALS114A

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