SN54ALS113A, SN74ALS113A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET

SDAS200 - D2661, APRIL 1982 - REVISED MAY 1986

features

Fully Buffered to Offer Maximum isolation from External Disturbance
Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
Dependable Texas Instruments Quality and Reliability

description

These devices contain two independent J-K negative-edge-triggeredflip-flops. A low level at the Preset input sets the outputsregardless of the levels of the other inputs. When Preset is inactive (high), data at the Jand K inputs meeting the setup time requirements are transferred tothe outputs on the negative-going edge of the clock pulse. Clocktriggering occurs at a voltage level and is not directly related tothe fall time of the clock pulse. Following the hold time interval,data at the J and K inputs may be changed without affecting thelevels at the outputs. These versatile flip-flops can perform astoggle flip-flops by tying J and K high.

The SN54ALS113A is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ALS113A is characterized for operation from 0°C to70°C.

Title: DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET
Product Family: OTHER FLIP-FLOPS
Device Functionality: FLIP-FLOP
Orderable Devices: SN74ALS113AD, SN74ALS113ADR, SN74ALS113AN

View the complete PDF datasheet: sdas200.pdf (54 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALS113A

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.