SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SDAS199A - APRIL 1982 - REVISED DECEMBER 1994

features

• Fully Buffered to Offer Maximum Isolation From External Disturbance
• Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

description

These devices contain two independent J-K negative-edge-triggeredflip-flops. A low level at the preset () or clear () inputs sets or resets theoutputs, regardless of the levels of the other inputs. When and are inactive (high), data at the Jand K inputs meeting the setup-time requirements is transferred tothe outputs on the negative-going edge of the clock pulse (CLK).Clock triggering occurs at a voltage level and is not directlyrelated to the fall time of the clock pulse. Following the hold-timeinterval, data at the J and K inputs may be changed without affectingthe levels at the outputs. These versatile flip-flops can perform astoggle flip-flops by tying J and K high.

The SN54ALS112A is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ALS112A is characterized for operation from 0°C to70°C.

View more information about generic part numbers:SN54ALS112A, SN74ALS112A

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