SDAS183A - DECEMBER 1982 - REVISED JUNE 1990
These Advanced Schottky devices are capable of performinghigh-speed arithmetic or logical comparisons on two 8-bit binary ortwo's complement words. Three fully decoded decisions about words Pand Q are externally available at the outputs. These devices arefully expandable to any word length by connecting the totem poleP>Q and P<Q outputs of each stage to theP>Q and P<Q inputs of the next higher-order stage. Thecascading paths are implemented with only a two-gate-level delay toreduce overall comparison times for long words. Theopen-collector P=Q output may be wire-ANDed together.
Both input words P and Q plus all three outputs (P>Q, P<Q,and P = Q) are equipped with latches to provide the designer withtemporary data storage for avoiding race conditions. The enablecircuitry is implemented with minimal delay times to enhanceperformance when the devices are cascaded for longer word lengths.Each latch is transparent when the appropriate latch enable, PLE,QLE, or OLE is high.
The enable inputs PLE and QLE and data inputs P and Q utilize pnpinput transistors to reduce the low-level input current requirementto typically -0.25 mA, which minimizes loading effects.
The Q register may be cleared to zero for a fast comparison of theP word to zero.
The SN54AS866 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74AS866A is characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN74AS866A
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