SDAS182 - APRIL 1990
IMPACT-X is a trademark of Texas Instruments Incorporated.
This 576-bit memory uses advanced low-power SchottkyIMPACT-XTM technology and features high speed and fastfall-through times. It consists of two FIFOs organized as 32 words by9 bits each.
A FIFO memory is a storage device that allows data to be writteninto and read from its array at independent data rates. These FIFOsare designed to process data at rates from 0 to 40 MHz in abit-parallel format, word by word.
The SN74ALS2238 consists of bus-transceiver circuits, two 32× 9 FIFOs, and control circuitry arranged for multiplexedtransmission of data directly from the data bus or from the internalFIFO memories. Enables GAB and GBA are provided to control thetransceiver functions. The SAB and SBA control pins are provided toselect whether real-time or stored data is transferred. The circuitryused for select control eliminates the typical decoding glitch thatoccurs in a multiplexer during the transition between stored andreal-time data. A low level selects real-time data and a high selectsstored data. Eight fundamental bus-management functions can beperformed as shown in Figure 1.
Data on the A or B data bus, or both, is written into the FIFOs ona low-to-high transition at the load clock (LDCKA or LDCKB) input andis read out on a low-to-high transition at the unload clock (UNCKA orUNCKB) input. The memory is full when the number of words clocked inexceeds, by the defined depth, the number of words clocked out.
When the memory is full, LDCK signals have no effect on the dataresiding in memory. When the memory is empty, UNCK signals have noeffect.
Status of the FIFO memories is monitored by the
,
, and are definable full flags. A high-to-low transition on
stores the binary value of A0through A4 into a register for use as the value of X. A high-to-lowtransition on 
stores thebinary value of B0 through B4 into a register for use as the value ofY. In this way, the depth of either FIFO can be defined to be one to32 words deep. The value of X and Y must be defined after power up orthe stored value of X and Y will be ambiguous. The outputs are low when their corresponding memories arefull and high when the memories are not full.
The and
A low-level pulse on the
or
inputs resets the control pointerson FIFO A or FIFO B and also sets low and highor 
low and at alow level, a low-level pulse on setsFIFO A to a depth of 32 - X, where X is the value stored above. Withat a high level, a low level pulseon sets FIFO A toa depth of 32 words. The depth of FIFO B is set in a similar manner.The first low-to-high transition on LDCKA or LDCKB, either after areset pulse or from an empty condition, will cause to go high and the data to appear on the Q outputs. Itis important to note that the first word does not have to beunloaded. Cascading is easily accomplished in the word-widthdirection, but is not possible in the word-depth direction.
The SN74ALS2238 is characterized for operation from 0°C to70°C.
View more information about generic part numbers:SN74ALS2238
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