SDAS163 - D2661, DECEMBER 1982 - REVISED JANUARY 1989
These 8-bit latches feature three-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are transparent D-type latches. While the enable (C) is high the Q outputs will follow the complements of data (D) inputs. When the enable is taken low the output will be latched at the inverses of the levels that were set up at the D inputs.
A buffered output-control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high-logic level provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components.
The output control (OC) does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS563A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS563B is characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN54ALS563A, SN74ALS563B
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