SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER

SDAS156C - APRIL 1982 - REVISED DECEMBER 1994

features

• Synchronous Load
• Direct Overriding Clear
• Parallel-to-Serial Conversion
• Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs

description

The SN74ALS166 parallel-load 8-bit shift register is compatiblewith most other TTL logic families. All inputs are buffered to lowerthe drive requirements. Input clamping diodes minimize switchingtransients and simplify system design.

These parallel-in or serial-in, serial-out registers have acomplexity of 77 equivalent gates on a monolithic chip. They featuregated clocks (CLK and CLK INH) inputs and an overriding clear () input. The parallel-in orserial-in modes are established by the shift/load (SH/) input. When high, SH/ enables the serial data (SER)input and couples the eight flip-flops for serial shifting with eachclock pulse. When low, the parallel (broadside) data (A-H) inputs areenabled and synchronous loading occurs on the next clock pulse.During parallel loading, serial data flow is inhibited. Clocking isaccomplished on the low-to-high-level edge of the clock pulse througha two-input positive-NOR gate permitting one input to be used as aclock-enable or clock-inhibit function. Holding either of the clockinputs high inhibits clocking; holding either low enables the otherclock input. This allows the system clock to be free running and theregister can be stopped on command with the clock input. CLK INHshould be changed to the high level only when CLK is high. Thebuffered overrides allother inputs, including CLK, and sets all flip-flops to zero.

The SN74ALS166 is characterized for operation from 0°C to70°C.

View more information about generic part numbers:SN74ALS166

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