SDAS146B - JANUARY 1986 - REVISED JANUARY 1995
These 9-bit flip-flops feature 3-state outputs designedspecifically for driving highly capacitive or relativelylow-impedance loads. They are particularly suitable for implementingwider buffer registers, I/O ports, bidirectional bus drivers, paritybus interfacing, and working registers.
With the clock-enable (
)input low, the nine D-type edge-triggered flip-flops enter data onthe low-to-high transitions of the clock (CLK) input. Taking 
)input low causes the nine Q outputs to go low independently of theclock.
A buffered output-enable (
) input places the nine outputs in either a normal logicstate (high or low logic levels) or a high-impedance state. Theoutputs also are in the high-impedance state during power-up andpower-down conditions. The outputs remain in the high-impedance statewhile the device is powered down. In the high-impedance state, theoutputs neither load nor drive the bus lines significantly. Thehigh-impedance state and increased drive provide the capability todrive bus lines without interface or pullup components.
does not affectthe internal operation of the flip-flops. Old data can be retained ornew data can be entered while the outputs are in the high-impedancestate.
The SN54ALS29823 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ALS29823 is characterized for operation from 0°C to70°C.
View more information about generic part numbers:SN54ALS29823, SN74ALS29823
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