SN54ALS74A, SN54AS74, SN74ALS74A, SN74AS74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SDAS143A - D2661, APRIL 1982 - REVISED SEPTEMBER 1987

features

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  TYPE	TYPICAL MAXIMUM CLOCK FREQUENCY (CL = 50 pF)	TYPICAL POWER DISSIPATION PER FLIP-FLOP
  'ALS74A	50 MHz	6 mW
  'AS74	134 MHz	26 mW

description

These devices contain two independent D-type positive-edge triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54ALS74A and SN54AS74 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74 are characterized for operation from 0°C to 70°C.

The output levels in this configuration are not guaranteed to meet the minimum levels for V_OH if the lows at Preset and Clear are near V_IL maximum. Furthermore, this configuration is nonstable; that is, it will not persist when Preset or Clear; returns to their inactive (high) level.

View more information about generic part numbers:SN54AS74, SN74AS74

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