SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SDAS119D - FEBRUARY 1987 - REVISED JANUARY 1995

features

Functionally Similar to AMD's AM29833
High-Speed Bus Transceiver With Parity Generator/Checker
Parity-Error Flag With Open-Collector Outputs
Register for Storing the Parity-Error Flag
Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs

description

The SN74ALS29833 is an 8-bit to 9-bit parity transceiver designedfor two-way communication between data buses. When data istransmitted from the A bus to the B bus, a parity bit is generated.When data is transmitted from the B bus to the A bus with itscorresponding parity bit, the parity-error () output indicates whether or notan error in the B data has occurred. The output-enable (OEA\, OEB\)inputs can be used to disable the device so that the buses areeffectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY)output and monitors the parity of the I/O ports with anopen-collector flag. is clocked into the register on therising edge of the clock (CLK) input. The error-flag register iscleared with a low pulse on the clear () input. When both and are low, data is transferred fromthe A bus to the B bus and inverted parity is generated. Invertedparity is a forced error condition that gives the designer moresystem diagnostic capability.

The SN74ALS29833 is characterized for operation from 0°C to70°C.

Title: 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
Product Family: PARITY TRANSCEIVERS
Device Functionality: BUS TRANSCEIVERS
Orderable Devices: SN74ALS29833DW, SN74ALS29833DWR, SN74ALS29833NT

View the complete PDF datasheet: sdas119d.pdf (96 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALS29833

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