SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SDAS118C - FEBRUARY 1987 - REVISED JANUARY 1995

features

• Functionally Similar to AMD's AM29854
• High-Speed Bus Transceiver With Parity Generator/Checker
• Parity-Error Flag With Open-Collector Outputs
• Latch for Storing the Parity-Error Flag
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs

description

The SN74ALS29854 is an 8-bit to 9-bit parity transceiver designedfor two-way communication between data buses. When data istransmitted from the A bus to the B bus, a parity bit is generated.When data is transmitted from the B bus to the A bus with itscorresponding parity bit, the parity-error () output indicates whether or notan error in the B data has occurred. The output-enable (, ) inputs can be used to disable the device so that thebuses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY)output and monitors the parity of the I/O ports with anopen-collector flag. canbe either passed, sampled, stored, or cleared from the latch usingthe latch-enable () and clear() controlinputs. When both OEA\ and OEB\ are low, data is transferred from theA bus to the B bus and inverted parity is generated. Inverted parityis a forced error condition that gives the designer more systemdiagnostic capability.

The SN74ALS29854 is characterized for operation from 0°C to70°C.

View more information about generic part numbers:SN74ALS29854

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