SN54AS867, SN54AS869 SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS

SDAS115C - DECEMBER 1982 - REVISED JANUARY 1995

features

• Fully Programmable With Synchronous Counting and Loading
• SN74ALS867A and ´AS867 Have Asynchronous Clear; SN74ALS869 and ´AS869 Have Synchronous Clear
• Fully Independent Clock Circuit Simplifies Use
• Ripple-Carry Output for n-Bit Cascading
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

description

These synchronous, presettable, 8-bit up/down counters featureinternal-carry look-ahead circuitry for cascading in high-speedcounting applications. Synchronous operation is provided by havingall flip-flops clocked simultaneously so that the outputs changecoincidentally with each other when so instructed by the count-enable(,) inputs and internal gating. Thismode of operation eliminates the output counting spikes normallyassociated with asynchronous (ripple-clock) counters. A bufferedclock (CLK) input triggers the eight flip-flops on the rising(positive-going) edge of the clock waveform.

These counters are fully programmable; they may be preset to anynumber between 0 and 255. The load-input circuitry allows parallelloading of the cascaded counters. Because loading is synchronous,selecting the load mode disables the counter and causes the outputsto agree with the data inputs after the next clock pulse.

The carry look-ahead circuitry provides for cascading counters forn-bit synchronous applications without additional gating. Twocount-enable (and ) inputs and a ripple-carry () output are instrumental inaccomplishing this function. Both and must be low tocount. The direction of the count is determined by the levels of theselect (S0, S1) inputs as shown in the function table. is fed forward to enable . thus enabled produces a low-level pulse while the countis zero (all outputs low) counting down or 255 counting up (alloutputs high). This low-level overflow-carry pulse can be used toenable successive cascaded stages. Transitions at and are allowed regardless of the levelof CLK. All inputs are diode clamped to minimize transmission-lineeffects, thereby simplifying system design.

These counters feature a fully independent clock circuit. With theexception of the asynchronous clear on the SN74ALS867A and´AS867, changes at S0 and S1 that modify the operating mode haveno effect on the Q outputs until clocking occurs. For the ´AS867and ´AS869, any time ENP\ and/or ENT\ is taken high, either goes or remains high. Forthe SN74ALS867A and SN74ALS869, any time is taken high, either goes or remains high. Thefunction of the counter (whether enabled, disabled, loading, orcounting) is dictated solely by the conditions meeting the stablesetup and hold times.

The SN54AS867 and SN54AS869 are characterized for operation overthe full military temperature range of -55°C to 125°C. TheSN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterizedfor operation from 0°C to 70°C.

View more information about generic part numbers:SN54AS867, SN54AS869, SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869

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