SDAS098B - OCTOBER 1984 - REVISED JANUARY 1995
These 8-bit latches are designed specifically for storing thecontents of the input data bus and providing the capability ofreading back the stored data onto the input data bus. The Q outputsare designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-hightransition of the clock (CLK) input when the enable (
low. When EN\ is high, both theread-back and write modes are disabled. Transitions on
The polarity of the Q outputs can be controlled by the polarity(T/C\) input. When T/C\ is high, Q is the same as is stored in theflip-flops. When T/C\ is low, the output data is inverted. The Qoutputs can be placed in the high-impedance state by taking theoutput-enable (
) input high. does notaffect the internal operation of the register. Old data can beretained or new data can be entered while the outputs are off.
A low level at the clear (
)input resets the internal registers low. The clear function isasynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standardversion, except that the recommended maximum IOL for the-1 version is increased to 48 mA. There is no -1 version of theSN54ALS996.
The SN54ALS996 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ALS996 is characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN54ALS996, SN74ALS996
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