SN54AS286, SN74AS286 9-BIT PARITY GENERATORS/CHECKERSWITH BUS-DRIVER PARITY I/O PORT

SDAS050B - DECEMBER 1983 - REVISED DECEMBER 1994

features

• Generate Either Odd or Even Parity forNine Data Lines
• Cascadable for n-Bit Parity
• Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
• Glitch-Free Bus During Power Up/Down
• Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

description

The SN54AS286 and SN74AS286 universal 9-bit paritygenerators/checkers feature a local output for parity checking and a48-mA bus-driving parity input/output (I/O) port for parity generation/checking. Theword-length capability is easily expanded by cascading.

The transmit () control inputis implemented specifically to accommodate cascading. When is low, the parity tree isdisabled and PARITY ERROR remains at a high logic level regardless ofthe input levels. When ishigh, the parity tree is enabled. PARITY ERROR indicates a parityerror when either an even number of inputs (A-I) are high and PARITYI/O is forced to a low logic level, or when an odd number of inputsare high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O portremains in the high-impedance state during power up or power down toprevent bus glitches.

The SN54AS286 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The SN74AS286is characterized for operation from 0°C to 70°C.

View more information about generic part numbers:SN54AS286, SN74AS286

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