SDAS039F - DECEMBER 1983 - REVISED JANUARY 1995
These devices consist of bus-transceiver circuits with 3-state oropen-collector outputs, D-type flip-flops, and control circuitryarranged for multiplexed transmission of data directly from the databus or from the internal storage registers. Data on the A or B bus isclocked into the registers on the low-to-high transition of theappropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates thefour fundamental bus-management functions that can be performed withthe octal bus transceivers and registers.
Output-enable (
) anddirection-control (DIR) inputs control the transceiver functions. Inthe transceiver mode, data present at the high-impedance port may bestored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored andreal-time (transparent mode)
data. The circuitry used for select control eliminates the typicaldecoding glitch that occurs in a multiplexer during the transitionbetween stored and real-time data. DIR determines which bus receivesdata when is low. In theisolation mode ( high), A datamay be stored in one register and/or B data may be stored in theother register.
When an output function is disabled, the input function is stillenabled and can be used to store and transmit data. Only one of thetwo buses, A or B, may be driven at a time.
The -1 version of the SN74ALS646A is identical to the standardversion, except that the recommended maximum IOL in the -1version is increased to 48 mA. There are no -1 versions of theSN54ALS646, SN54ALS648, or SN74ALS648A.
The SN54ALS646, SN54ALS648, and SN54AS646 are characterized foroperation over the full military temperature range of -55°C to125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648are characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN54ALS646, SN54ALS648, SN54AS646, SN74ALS646A, SN74ALS646A-1, SN74ALS648A, SN74AS646, SN74AS648
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