SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCLS389B - SEPTEMBER 1997 - REVISED APRIL 1998

features

EPIC^TM (Enhanced-Performance Implanted CMOS) Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and 300-mil DIPs (J)
EPIC is a trademark of Texas Instruments Incorporated.

description

These quadruple 2-input positive-NAND gates are designed for 2-V to 5.5-V V_CC operation.

The 'LV00A devices perform the Boolean function Y = A \•\ B\ or Y = A\ + B\ in positive logic.

The SN54LV00A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV00A is characterized for operation from -40°C to 85°C.

Title: QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Product Family: NAND
Device Functionality: 2-INPUT POSITIVE-NAND GATES
Orderable Devices: SN74LV00ADGVR

View the complete PDF datasheet: scls389b.pdf (115 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LV00A

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