SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS381C - AUGUST 1997 - REVISED MAY 1998

features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and 300-mil DIPs (J)

  EPIC is a trademark of Texas Instruments Incorporated.

description

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V V_CC operation.

A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The SN54LV74A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV74A is characterized for operation from -40°C to 85°C.

^† This configuration is unstable; that is, it does not persist when PRE\ or CLR\ returns to its inactive (high) level.

View more information about generic part numbers:SN74LV74A

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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