SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

SCLS195B - FEBRUARY 1993 - REVISED APRIL 1996

features

EPIC^TM (Enhanced-Performance Implanted CMOS) 2-Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs

description

These octal D-type flip-flops are designed for 2.7-V to 5.5-VV_CC operation.

The 'LV273 are positive-edge-triggered flip-flops with directclear () input.Information at the data (D) inputs meeting the setup timerequirements is transferred to the Q outputs on the positive-goingedge of the clock pulse. Clock triggering occurs at a particularvoltage level and is not directly related to the transition time ofthe positive-going pulse. When the clock (CLK) input is at either thehigh or low level, the D-input signal has no effect at the output.

The SN74LV273 is available in TI's shrink small-outline package(DB), which provides the same I/O pin count and functionality ofstandard small-outline packages in less than half theprinted-circuit-board area.

The SN54LV273 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The SN74LV273is characterized for operation from -40°C to 85°C.

Title: OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
Product Family: D-TYPE FLIP-FLOPS
Device Functionality: D-TYPE
Orderable Devices: SN74LV273DBLE, SN74LV273DW, SN74LV273DWR, SN74LV273PWLE

View the complete PDF datasheet: scls195b.pdf (129 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LV273

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