SCLS190D - FEBRUARY 1993 - REVISED JULY 1996
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These 3-line to 8-line decoders/demultiplexers are designed for2.7-V to 5.5-V VCC operation.
The 'LV138 are designed for high-performance memory-decoding ordata-routing applications requiring very short propagation delaytimes. In high-performance memory systems, this decoder can be usedto minimize the effects of system decoding. When employed withhigh-speed utilizing a fast enable circuit, the delay times of thisdecoder and the enable time of the memory are usually less than thetypical access time of the memory. This means that the effectivesystem delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enableinputs select one of eight output lines. Two active-low and oneactive-high enable inputs reduce the need for external gates orinverters when expanding. A 24-line decoder can be implementedwithout external inverters and a 32-line decoder requires only oneinverter. An enable input can be used as a data input fordemultiplexing applications.
The SN74LV138 is available in TI's shrink small-outline package(DB), which provides the same I/O pin count and functionality ofstandard small-outline packages in less than half theprinted-circuit-board area.
The SN54LV138 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The SN74LV138is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN74LV138
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