SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS189C - FEBRUARY 1993 - REVISED APRIL 1996

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features

EPIC^TM (Enhanced-Performance Implanted CMOS) 2- Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs
EPIC is a trademark of Texas Instruments Incorporated.

description

These dual positive-edge-triggered D-type flip-flops are designedfor 2.7-V to 5.5-V V_CC operation.

A low level at the preset () or clear ()inputs sets or resets the outputs regardless of the levels of theother inputs. When and are inactive (high), data at thedata (D) inputs meeting the setup-time requirements is transferred tothe

outputs on the positive-going edge of the clock pulse. Clocktriggering occurs at a voltage level and is not directly related tothe rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels atthe outputs.

The SN74LV74 is available in TI's shrink small-outline package(DB), which provides the same I/O pin count and functionality ofstandard small-outline packages in less than half theprinted-circuit-board area.

The SN54LV74 is characterized for operation over the full militarytemperature range of -55°C to 125°C. The SN74LV74 ischaracterized for operation from -40°C to 85°C.

Title: DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
Product Family: D-TYPE FLIP-FLOPS
Device Functionality: D-TYPE
Orderable Devices: SN74LV74D, SN74LV74DBLE, SN74LV74DR, SN74LV74PWLE

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View more information about generic part numbers:SN74LV74

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