SCLS171C - MARCH 1984 - REVISED MAY 1997
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The 'HCT138 are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G\) and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The SN54HCT138 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74HCT138 is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN54HCT138, SN74HCT138
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