SCLS145B - DECEMBER 1982 - REVISED MAY 1997
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.
A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54HC563 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74HC563 is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN74HC563
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.