SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

SCES125A - FEBRUARY 1998 - REVISED MARCH 1998

features

Member of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
Ideal for Use in PC100 Register DIMM
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

description

This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ALVC16835 is characterized for operation from -40°C to 85°C.

^† Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low

Title: 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS DRIVERS (UBDS)
Device Functionality: 18-BIT UNIVERSAL BUFFER/DRIVER
Orderable Devices: SN74ALVC16835DGGR, SN74ALVC16835DGVR, SN74ALVC16835DL, SN74ALVC16835DLR

View the complete PDF datasheet: sces125a.pdf (106 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVC16835

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