SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SCES124C - DECEMBER 1997 - REVISED MAY 1998

features

EPIC^TM (Enhanced-Performance Implanted CMOS) Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and 300-mil DIPs (J)
EPIC is a trademark of Texas Instruments Incorporated.

description

The `LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V V_CC operation.

These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE\) input is high.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54LV125A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV125A is characterized for operation from -40°C to 85°C.

Title: QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
Product Family: NON INVERTERS
Device Functionality: QUADRUPLE BUS BUFFER GATE
Orderable Devices: SN74LV125ADGVR

View the complete PDF datasheet: sces124c.pdf (129 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LV125A

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