SN74ALVCHR162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCES123C - SEPTEMBER 1997 - REVISED DECEMBER 1997

features

Member of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and 300-mil Shrink Small-Outline (DL) Packages

Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.

description

This 18-bit universal bus transceiver is designed for 2.3-V to 3.6-V V_CC operation.

The SN74ALVCHR162601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA, and CLKENBA\.

The outputs include equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCHR162601 is characterized for operation from -40°C to 85°C.

Title: 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Product Family: STANDARD TRANSCEIVERS
Device Functionality: 18-BIT BUS TRANSCEIVER
Orderable Devices: SN74ALVCHR162601DGGR, SN74ALVCHR162601DGVR, SN74ALVCHR162601DLR

View the complete PDF datasheet: sces123c.pdf (117 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVCHR162601

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