SCES058C - NOVEMBER 1995 - REVISED OCTOBER 1997
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This 18-bit universal bus transceiver is designed for 2.3-V to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENAB\ and CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single register. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKEN\ inputs are low. The A-to-B data transfer is synchronized to the CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA and CLK2BA inputs.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162525 is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN74ALVCH162525
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