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Data Sheet Abstract

SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCES024B - JULY 1995 - REVISED AUGUST 1997


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features

description

This 18-bit universal bus transceiver is designed for 2.3-V to 3.6-V VCC operation.

Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA\ is active low).

To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16501 is characterized for operation from -40°C to 85°C


Title: 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: 18-BIT BUS TRANSCEIVER
Orderable Devices: SN74ALVCH16501DGGR, SN74ALVCH16501DL, SN74ALVCH16501DLR

View the complete PDF datasheet: sces024b.pdf (121 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVCH16501

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