SCES022D - JULY 1995 - REVISED JANUARY 1998
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This 9-bit, 4-port universal bus exchanger is designed for 2.3-V to 3.6-V VCC operation.
The SN74ALVCH16409 allows synchronous data exchange between four different buses. Data flow is controlled by the select (SEL0-SEL4) inputs. A data-flow state is stored on the rising edge of the clock (CLK) input if the select-enable (SELEN\) input is low. Once a data-flow state has been established, data is stored in the flip-flop on the rising edge of CLK if SELEN\ is high.
The data-flow control logic is designed to allow glitch-free data transmission.
When preset (PRE\) transitions high, the outputs are disabled immediately without waiting for a clock pulse. To leave the high-impedance state, both PRE\ and SELEN\ must be low and a clock pulse must be applied.
To ensure the high-impedance state during power up or power down, PRE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16409 is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN74ALVCH16409
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