SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SCES018D - AUGUST 1995 - REVISED SEPTEMBER 1997

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Member of the Texas Instruments Widebus^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

  EPIC and Widebus are trademarks of Texas Instruments Incorporated.

description

This 12-bit to 24-bit registered bus exchanger is designed for 2.3-V to 3.6-V V_CC operation.

The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus.

The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN\) inputs are low. The select (SEL\) line is synchronous with CLK and selects 1B or 2B input data for the A outputs.

For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). These control terminals are registered so bus direction changes are synchronous with CLK.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162268 is characterized for operation from -40°C to 85°C.

View more information about generic part numbers:SN74ALVCH162268

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
Trademarks, Important Notice!