SCES007B - MARCH 1995 - REVISED APRIL 1996
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The 'LV165 parallel-load, 8-bit shift registers are designed for2.7-V to 5.5-V VCC operation.
When the device is clocked, data is shifted toward the serialoutput QH. Parallel-in access to each stage is provided byeight individual direct data inputs that are enabled by a low levelat the SH/
input. The'LV165 feature a clock inhibit function and a complemented serialoutput Q\H.
Clocking is accomplished by a low-to-high transition of the clock(CLK) input while SH/ isheld high and clock inhibit (CLK INH) is held low. The functions ofthe CLK and CLK INH inputs are interchangeable. Since a low CLK inputand a low-to-high transition of CLK INH accomplishes clocking, CLKINH should be changed to the high level only while CLK is high.Parallel loading is inhibited when SH/ is held low independently of the levels of CLK, CLKINH, or SER.
The SN54LV165 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The SN74LV165is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN74LV165
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