SN54LV125, SN74LV125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SCES003B - NOVEMBER 1994 - REVISED APRIL 1996

features

EPIC^TM (Enhanced-Performance Implanted CMOS) 2-u Process
Typical V_OLP (Output Ground Bounce)< 0.8 V at V_CC, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot > 2 V at V_CC, T_A = 25°C
ESD Protection Exceeds 2000 V per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs
EPIC is a trademark of Texas Instruments Incorporated.

description

These quadruple bus buffer gates are designed for 2.7-V to 5.5-VV_CC operation.

The 'LV125 feature independent line drivers with 3-state outputs.Each output is disabled when the associated output-enable () input is high.

The SN54LV125 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The SN74LV125is characterized for operation from -40°C to 85°C.

Title: QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
Product Family: INVERTERS
Device Functionality: BUFFER/DRIVER
Orderable Devices: SN74LV125D, SN74LV125DBLE, SN74LV125DR, SN74LV125PWLE

View the complete PDF datasheet: sces003b.pdf (107 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LV125

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