SN54LVTH16500, SN74LVTH16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS701B - JULY 1997 - REVISED MARCH 1998

features

Members of the Texas Instruments Widebus^TM Family
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
High-Impedance State During Power Up and Power Down
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Power Off Disables Outputs, Permitting Live Insertion
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus and UBT are trademarks of Texas Instruments Incorporated.

description

The 'LVTH16500 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB\ and CLKBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\. Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, and CLKBA\. The output enables are complementary (OEAB is active high and OEBA\ is active low).

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

The SN54LVTH16500 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16500 is characterized for operation from -40°C to 85°C.

^† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA\, LEBA, and CLKBA\.

^‡ Output level before the indicated steady-state input conditions were established

^§ Output level before the indicated steady-state input conditions were established, provided that CLKAB\ was low before LEAB went low

Title: 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Product Family: STANDARD TRANSCEIVERS
Device Functionality: 18-BIT BUS TRANSCEIVER

View the complete PDF datasheet: scbs701b.pdf (118 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVTH16500

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