SN54LVTH16646, SN74LVTH16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS698D - JULY 1997 - REVISED APRIL 1998

features

• Members of the Texas Instruments Widebus^TM Family
• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down to 2.7 V
• High-Impedance State During Power Up and Power Down
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Power Off Disables Outputs, Permitting Live Insertion
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus is a trademark of Texas Instruments Incorporated.

description

The 'LVTH16646 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'LVTH16646 devices.

Output-enable (OE\) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54LVTH16646 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16646 is characterized for operation from -40°C to 85°C.

^† The data-output functions may be enabled or disabled by various signals at OE\ or DIR. Data-input functions always are enabled, i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

Figure 1. Bus-Management Functions

View more information about generic part numbers:SN74LVTH16646

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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